Modern integrated circuits are required to operate at very high clock signal frequencies over a large range of environmental conditions.
Power supply noises can affect the performance of an integrated circuit. Power supply noises can affect the timing of periodic signals (such as but not limited to clock signals) generated by the integrated circuit or by a module (such as a phase locked loop (PLL) of the integrated circuit.
The relationship between power supply noises and the timing of clock signals of an integrated circuit is not known in advance and is also responsive to various processing parameters.
Noise immunity can be tested by controllable modulation (delay adjustment) of the position of the clock signal edges (the process is also referred to as clock jitter insertion). These tests require a tedious calibration sequence during which the relationship between the delay period and a power supply noise is calibrated.
There is a need to provide an efficient method and device for testing the noise immunity of an integrated circuit.